How AI Chips Like Nvidia's GPUs Are Designed and Manufactured

Nvidia shares fell more than 3% on a Wednesday in October 2026 and slipped further in pre-market trading the next day, as a hotter-than-expected US inflation reading pushed up bond yields and triggered a broader sell-off in chip stocks, according to Yahoo Finance. The same report said cloud provider CoreWeave dropped more than 16% on concerns about its debt load, that Marvell Technology and SK Hynix also fell amid separate worries about Chinese competition, and that investors were awaiting TSMC's quarterly results, expected to show a 60% rise in profit.

The sell-off was tied to interest-rate and debt worries rather than to any change in how AI chips are made or sold. But it has drawn fresh attention to the industry behind the chips themselves — a process split between two very different businesses: designing a chip, and manufacturing it.

Design: drawing the circuit before anything is built

Companies such as Nvidia do not operate their own chip factories. Under the "fabless" model, Nvidia designs chip architecture and software — such as its CUDA platform — and relies on outside foundries for production, according to the Institute for AI Policy and Strategy (IAPS). The Motley Fool describes Nvidia's GPUs as the hardware that performs the training and inference work behind AI models.

IAPS explains that chip design starts with high-level requirements, which architects turn into detailed circuit logic using electronic design automation (EDA) software. Designers either build components from scratch or license ready-made "IP cores," then simulate and formally verify the design before it is translated into manufacturing files matched to a specific foundry's process. IAPS states that "chip design is a difficult and laborious process," noting that designers such as Nvidia and AMD employ tens of thousands of people and that designing a cutting-edge AI chip can take a year or longer.

Manufacturing: hundreds of steps on a silicon wafer

Once a design is finished, it moves to a foundry — most often Taiwan's TSMC for the most advanced AI chips. Manufacturing begins with highly purified 300mm silicon wafers and a set of photomasks that encode the circuit pattern, per IAPS. Building the chip itself involves hundreds of repeated steps: depositing material layers, patterning them with light-sensitive photoresist exposed through the masks (photolithography), doping sections with ion implantation to set their electrical properties, polishing the surface flat, and adding metal layers to wire the components together.

The lithography step depends on extreme ultraviolet (EUV) machines made exclusively by the Dutch company ASML. Reporting its third-quarter 2026 results on October 14, ASML said sales reached €11.7 billion, up 55% year-on-year, with net income more than doubling to €5 billion, according to Euronews. Despite record sales and a raised 2026 outlook, ASML said its planned 30%-a-year capacity increases for 2027 and 2028 will still not be enough to meet customer orders. ASML chief executive Christophe Fouquet said customers are now booking machines years in advance.

Packaging has become the new bottleneck

After a wafer is fabricated, it is cut into individual dies, tested, and assembled into a finished package — a stage IAPS calls Assembly, Test and Packaging (ATP). For AI chips, this step now matters as much as fabrication itself. TSMC uses a technique called Chip-on-Wafer-on-Substrate (CoWoS) to stack a processor die together with several stacks of high-bandwidth memory on one interposer, which IAPS says TSMC applies to Nvidia's H100 chips. TSMC's own October 2026 announcement of its roadmap, covering a next-generation A13 production node and expanded CoWoS packaging, said a future "14-reticle size" CoWoS format will integrate roughly ten large compute dies with about 20 HBM memory stacks by 2028.

TSMC's own roadmap announcement describes CoWoS advanced packaging as expanding to meet AI-driven demand, moving toward the 14-reticle format by 2028 and a further expansion in 2029. That trajectory points to a broader shift across the AI chip supply chain — from silicon fabrication toward packaging as a growing constraint — even as ASML, a maker of lithography tools rather than packaging equipment, continues to report record demand for its machines.

AI is also being used to build the chips

Nvidia and TSMC have begun applying AI tools inside the manufacturing process itself. According to Nvidia's own announcement, TSMC uses Nvidia's cuLitho software to accelerate computational lithography — the calculations needed to design photomasks — delivering what Nvidia describes as a 20–50% improvement in cost-effectiveness or cycle time compared with CPU-based methods. The companies also described using Nvidia's cuEST library for chemistry simulations, vision-AI tools for defect detection on the production line, and an early-stage virtual-factory project called "FabTwin," built on Nvidia's Omniverse platform, to test fab layouts before they are built.

Alternative designs to the standard GPU

Not every company follows Nvidia's architecture. The Motley Fool reports that Cerebras Systems builds a single giant chip — its Wafer-Scale Engine — that it describes as 58 times larger than Nvidia's B200 GPU, combining large amounts of compute and memory on one piece of silicon rather than linking many smaller chips together. Cerebras says this design produces inference speeds up to 15 times faster than GPU-based systems for some workloads, an approach the Fool frames as a direct design challenge to Nvidia's dominant position in AI hardware.